This disclosure relates to digital signal processing (“DSP”) circuitry, especially on integrated circuit (“IC”) devices. More particularly, the disclosure relates to such DSP circuitry that is adapted to perform finite-impulse-response (“FIR”) digital filtering.
DSP circuitry may be provided on an integrated circuit (“IC”) in the form of multiple instances (identical or substantially identical repetitions) of a “block” of DSP circuitry. Such a “DSP circuit block” (or “DSP block”) may be capable of several different DSP operations, and the block may be controllable to select which of the possible DSP operations the block performs in any particular application of the IC. For example, the IC may be a programmable logic device (“PLD”), a field-programmable gate array (“FPGA”), or other similar type of device that is manufactured as a relatively general-purpose product that a user can “customize” to perform the functions needed by that user's particular application of the device. Such customization may be by programming function control data into so-called configuration memory cells (configuration random access memory or “CRAM”) on the device. After having been thus programmed or configured, the IC can enter its normal or user mode of operation, in which it performs the functions (e.g., the DSP functions) it has been programmed or configured to perform. Manufacturing such an IC with DSP blocks that can satisfy any of a wide range of possible user needs increases the number of users who can use the IC for their particular applications. This increases the size of the market for the IC, which can benefit the manufacturer; but increased sales volume can also help to lower the unit cost of the IC, which can benefit users of the IC.
A particularly advantageous form of relatively general-purpose DSP block circuitry includes two multiplier circuits that can be used either separately or together. Such an advantageous DSP block may also include the ability to feed its outputs (i.e., results of DSP operations it has performed) directly or substantially directly into another instance of the same DSP block circuitry on the IC for further processing in that “another” DSP block (so-called output chaining). Examples of such advantageous DSP block circuitry are shown in commonly assigned, concurrently filed Streicher et al. U.S. patent application Ser. No. 12/716,878, which is hereby incorporated by reference herein in its entirety. The just-mentioned Streicher et al. document will sometimes be referred to herein as “the Streicher et al. reference.”
Among the possible applications of DSP block circuitry of the type mentioned above is in the performance of finite-impulse-response (“FIR”) digital filtering. FIR filtering typically involves passing successive input signal samples through a series of delay circuits, each of which delays each sample applied to it by the time duration of any one sample in the input sample stream. The just-mentioned “time duration” is typically the “period” or time duration of an “operating cycle” of the circuitry, or the period of a clock signal that is used to control the rate of such operating cycles. Each input sample and each sample output by each delay circuit in a given operating cycle of the circuitry is multiplied by a respective filter coefficient value, and all of the resulting multiplication products are added together to produce the output of the FIR filter for that operating cycle.
A possible problem associated with FIR filter circuitry is that it can take a relatively long time to complete the addition of a significant number of the above-mentioned multiplication product values. This can necessitate lengthening the operating cycle of the circuitry (accomplished by slowing down the clock that controls the speed of the circuitry). With the modern emphasis on rapid circuit operation, this can be undesirable.
As a possible way to ameliorate the adverse effects of long addition time, the so-called systolic form of FIR filter circuitry has been developed. This is circuitry with additional (“systolic”) delay in both the input sample delay chain and the product-summing chain. Because a user of DSP circuit blocks of the type mentioned above may want to use them to implement systolic form FIR filters, a need exists for efficient ways to include systolic delays (or registers) in such DSP blocks.
Providing DSP circuitry on an IC (especially ICs like PLDs, FPGAs, and the like) in the form of a plurality of DSP blocks (always meaning multiple instances of identical or substantially identical instances of DSP module circuitry) can be advantageous and desirable for several reasons. Among these reasons are design efficiency (e.g., because the design of one DSP block (or DSP module) can be replicated several times on the IC). Another benefit may be the ability of a user of the IC to put together (i.e., use in an interconnected way) any number of such DSP blocks on the IC to perform a DSP function that is larger than can be performed in one DSP block by itself. Only as many DSP blocks as are needed are thus put together, and any other DSP blocks on the IC remain available for other purposes. Still another advantage of DSP blocks is that they may include circuitry that is dedicated to performing DSP operations (rather than being more completely general-purpose circuitry). Such DSP block circuitry can therefore perform DSP operations more efficiently. However, if a DSP block is not optimized for implementing systolic FIR filters, it can be necessary to use circuitry outside of the DSP blocks to complete the systolic FIR filter implementation. For example, more general-purpose adder circuitry outside the DSP blocks may be needed to sum multiplication products output by multiple DSP blocks. Use of such more general-purpose adder circuitry, etc., outside of the DSP blocks can be inefficient. This leads to a need for DSP blocks that are better adapted for more completely implementing systolic FIR filters, especially systolic FIR filters that can be of any size and that can avoid use of general-purpose (“soft”) adder circuitry external to the DSP blocks.